Digital Electronics and Design with VHDL

Preface1. Introduction1.1 Historical notes1.2 Analog versus digital1.3 Bits, bytes, and words1.4 Digital Circuits1.5 Combinational circuits versus sequential circuits1.6 Integrated circuits (ICs)1.7 Printed circuit board (PCB)1.8 Logic values versus physical values1.9 Non-programmable, programmable, and hardware-programmable1.10 Binary waveforms1.11 DC, AC, and transient responses1.12 Programmable logic devices (PLDs)1.13 Circuit synthesis and simulation with VHDL1.14 Circuit simulation with Spice1.15 Gate-level versus transistor-level analysis2. Binary representations2.1 Binary code2.2 Octal and hexadecimal codes2.3 Gray code2.4 BCD code2.5 Codes for negative numbers2.6 Floating-point representation2.7 ASCII code2.8 Unicode2.9 Exercises3. Binary arithmetic3.1 Unsigned addition3.2 Signed addition and subtraction3.3 Shift operations3.4 Unsigned multiplication3.5 Signed multiplication3.6 Unsigned division3.7 Signed division3.8 Floating-point addition and subtraction3.9 Floating-point multiplication3.10 Floating-point division3.11 Exercises4. Introduction to digital circuits4.1 Introduction to MOS transistors4.2 Inverter and CMOS logic4.3 AND and NAND gates4.4 OR and NOR gates4.5 XOR and XNOR gates4.6 Modulo-2 adder4.7 Buffer4.8 Tri-state buffer4.9 Open-drain buffer4.10 D-type flip-flop4.11 Shift register4.12 Counters4.13 Pseudo-random sequence generator4.14 Exercises5. Boolean algebra5.1 Truth tables5.2 Minterms and SOP equations5.3 Maxterms and POS equations5.4 Standard circuits for SOP and POS equations5.5 Karnaugh maps5.6 Large Karnaugh maps5.7 Other function-simplification techniques5.8 Propagation delay and glitches 5.9 Exercises6. Line codes6.1 The use of line codes6.2 Parameters and types of line codes6.3 Unipolar codes6.4 Polar codes6.5 Bipolar codes6.6 Biphase/Manchester codes6.7 MLT codes6.8 mB/nB codes6.9 PAM codes6.10 Exercises7. Error-detecting/correcting codes7.1 Introduction7.2 Single-parity-check (SPC) codes7.3 Cyclic redundancy check (CRC) codes7.4 Hamming codes7.5 Reed Solomon codes7.6 Convolutional codes and Viterbi decoder7.7 Turbo codes7.8 Low-density parity-check (LDPC) codes7.9 Exercises8. Bipolar junction transistor (BJT)8.1 Semiconductors8.2 The bipolar junction transistor (BJT)8.3 I-V characteristics8.4 DC response8.5 Transient response8.6 AC response8.7 Modern BJTs8.8 Exercises9. NIS transistor9.1 Semiconductors9.2 The field-effect transistor (MOSFET)9.3 I-V characteristics9.4 DC response9.5 CMOS inverter9.6 Transient response9.7 AC response9.8 Modern MOSFETs9.9 Exercises10. Logic families and I/Os Logic architectures and I/Os10.1 BJT-based logic families10.2 Diode-transistor logic (DTL)10.3 Transistor-transistor logic (TTL)10.4 Emitter-coupled logic (ECL)10.5 MOS-based logic families10.6 CMOS logic10.7 Other static MOS architectures10.8 Dynamic MOS architectures10.9 Modern I/O standards10.10 Exercises11. Combinational logic circuits11.1 Combinational versus sequential logic11.2 Logical versus arithmetic circuits11.3 Fundamental logic gates11.4 Compound gates11.5 Encoders and decoders11.6 Multiplexer11.7 Parity detector11.8 Priority encoder11.9 Binary sorter11.10 Barrel shifters 11.11 Non-overlapping clock generators11.12 Short-pulse generators11.13 Schmitt triggers11.14 Memories11.15 Exercises11.16 Exercises with VHDL11.17 Exercises with SPICE12. Combinational arithmetic circuits12.1 Arithmetic versus logical functions12.2 Basic adders12.3 Fast adders12.4 Bit-serial adder12.5 Signed adders/subtracters12.6 Incrementer, decrementer, and two’s complementer12.7 Comparators12.8 ALU (arithmetic-logic unit)12.9 Multipliers12.10 Dividers12.11 Exercises12.12 Exercises with VHDL12.13 Exercises with SPICE13. Registers13.1 Sequential versus combinational logic13.2 SR latch (SRL)13.3 D latch (DL)13.4 D flip-flop (DFF)13.5 Master-slave DFFs13.6 Pulse-based DFFs13.7 Dual-edge DFFs13.8 Statistically low-power DFFs13.9 DFF control ports13.10 T flip-flop (TFF)13.11 Exercises13.12 Exercises with SPICE14. Sequential circuits14.1 Shift registers14.2 Synchronous counters14.3 Asynchronous counters14.4 Signal generators14.5 Frequency dividers14.6 PLL and prescalers14.7 Pseudo-random sequence generators14.8 Scramblers and descramblers14.9 Exercises14.10 Exercises with VHDL 14.11 Exercises with SPICE15. Finite state machines15.1 FSM model15.2 Design of finite state machines15.3 System resolution and glitches15.4 Design of large FSMs15.5 Design of FSMs with complex combinational logic15.6 Design of symmetric-phase frequency dividers15.7 FSM encoding styles15.8 Exercises15.9 Exercises with VHDL16. Volatile memories16.1 Memory types16.2 SRAM (Static Random Access Memory)16.3 Dual and Quad Data Rate SRAMS (DDR and QDR)16.4 DRAM (Dynamic Random Access Memory)16.5 SDRAM (Synchronous DRAM)16.6 Dual Data Rate SDRAMs, (DDR, DDR2, and DDR3)16.7 CAM (Content-Addressable Memory) for Cache Memories16.8 Exercises17. Non-volatile memories17.1 Memory types17.2 MP-OM (Mask-Programmed ROM)17.3 OTP ROM (One-Time Programmable ROM or PROM)17.4 EPROM (Electrically Programmable ROM)17.5 EEPROM (Electrically Erasable-Programmable ROM)17.6 Flash memory17.7 Next generation memories: FRAM, MRAM, PRAM17.8 Exercises18. Programmable logic devices (PLDs)18.1 The concept of programmable logic devices18.2 SPLDs18.3 CPLDs18.4 FPGAs18.5 Exercises19. VHDL Summary19.1 About VHDL19.2 Code structure19.3 Fundamental libraries and packages19.4 Pre-defined data types19.5 User-defined data types and arrays19.6 Operators19.7 Attributes19.8 Concurrent code (WHEN, GENERATE)19.9 Sequential code (IF, CASE, LOOP, WAIT)19.10 Objects (SIGNAL, VARIALBE, CONSTANT)19.11 Packages19.12 Components19.13 Functions19.14 Procedures19.15 VHDL template for FSMs19.16 Exercises20. VHDL design of combinational logic circuits20.1 Generic address decoder20.2 BCD-to-SSD conversion function20.3 Generic multiplexer20.4 Generic priority encoder20.5 Design of ROM memory20.6 Design of Synchronous RAM Memories20.7 Exercises21. VHDL design of combinational arithmetic circuits21.1 Carry-rippler adder21.2 Carry-lookahead adder21.3 Signed and unsigned adders/subtracters21.4 Signed and unsigned multipliers/dividers21.5 ALU21.6 Exercises22. VHDL design of regular sequential circuits22.1 Shift register with load22.2 Switch debouncer22.3 Timer22.4 Fibonacci series generator22.5 Frequency meters22.6 Neural networks22.7 Exercises23. VHDL design of state machines23.1 String detector23.2 “Universal” signal generator23.3 Car alarm23.4 LCD driver23.5 Exercises24. Simulation with VHDL testbenches24.1 synthesis versus simulation 24.2 Stimulus generation24.3 Writing testbenches—part 1 24.4 Writing testbenches—part 224.5 Functional simulations24.6 Timing Simulations24.7 Exercises25. Simulation with SPICE25.1 About SPICE25.2 Types of Analysis 25.3 Basic structure of SPICE code25.4 Declarations of electronic devices25.5 Declarations of independent DC sources25.6 Declarations of independent AC sources25.7 Declarations of dependent sources25.8 SPICE inputs and outputs25.9 DC respons examples25.10 Transient response examples25.11 AC response sample25.12 Subcircuits25.13 Exercises involving combinational logic circuits25.14 Exercises involving combinational arithmetic circuits25.15 Exercises involving registers25.16 Exercises involving sequential circuitsAppendicesA ModelSim TutorialB PSpice Tutorial ReferencesIndex